The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2009

Filed:

Jul. 15, 2008
Applicants:

Mario D. Nemirovsky, Saratoga, CA (US);

Adolfo M. Nemirovsky, San Jose, CA (US);

Narendra Sankar, Campbell, CA (US);

Enrique Musoll, San Jose, CA (US);

Inventors:

Mario D. Nemirovsky, Saratoga, CA (US);

Adolfo M. Nemirovsky, San Jose, CA (US);

Narendra Sankar, Campbell, CA (US);

Enrique Musoll, San Jose, CA (US);

Assignee:

MIPS Technologies, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.


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