The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2009

Filed:

Jan. 04, 2005
Applicants:

Kyoung-woo Lee, Seoul, KR;

Hong-jae Shin, Seoul, KR;

Jae-hak Kim, Seoul, KR;

Young-jin Wee, Seongnam-si, KR;

Seung-jin Lee, Suwon-si, KR;

Ki-kwan Park, Busan-si, KR;

Inventors:

Kyoung-Woo Lee, Seoul, KR;

Hong-Jae Shin, Seoul, KR;

Jae-Hak Kim, Seoul, KR;

Young-Jin Wee, Seongnam-si, KR;

Seung-Jin Lee, Suwon-si, KR;

Ki-Kwan Park, Busan-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.


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