The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
Jan. 24, 2006
Michael Hufford, Catonsville, MD (US);
Eric Naviasky, Ellicott City, MD (US);
Stephen Williams, Baltimore, MD (US);
Michelle Williams, Laurel, MD (US);
Michael Hufford, Catonsville, MD (US);
Eric Naviasky, Ellicott City, MD (US);
Stephen Williams, Baltimore, MD (US);
Michelle Williams, Laurel, MD (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A self-tuning 3order type III phase-locked loop (PLL) is disclosed. In one aspect, the PLL provides frequency control that is implemented in three (3) parallel paths. The PLL provides frequency response tracking using a number of elements including a triple control voltage-controlled oscillator (VCO), a frequency-to-current (F2I) converter, and a switched capacitor loop filter. In addition to compensation for feedback ratio variation, near constant F2I gain over process variations and switched capacitor filters synchronized to a reference signal, near constant VCO gain over process variations allows the open loop frequency response to be tailored to track the reference signal. A high-speed locking technique is employed which significantly reduces acquisition time in low bandwidth cases. This PLL may be fabricated in a 0.18 μm CMOS logic process.