The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
Feb. 09, 2008
Riichiro Takemura, Tokyo, JP;
Tomonori Sekiguchi, Tama, JP;
Satoru Akiyama, Sagamihara, JP;
Hiroaki Nakaya, Kokubunji, JP;
Masayuki Nakamura, Tokyo, JP;
Riichiro Takemura, Tokyo, JP;
Tomonori Sekiguchi, Tama, JP;
Satoru Akiyama, Sagamihara, JP;
Hiroaki Nakaya, Kokubunji, JP;
Masayuki Nakamura, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.