The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
Jul. 16, 2007
Kazuo Shimokawa, Yokohama, JP;
Takashi Koyanagawa, Yokohama, JP;
Masako Ooishi, Yokohama, JP;
Tatsuya Yamada, Yokohama, JP;
Osamu Usuda, Tatsuno, JP;
Yoshiki Endo, Ibo-gun, JP;
Taiki Miura, Ibo-gun, JP;
Masaki Toyoshima, Himeji, JP;
Ichiro Omura, Yokohama, JP;
Akio Nakagawa, Fujisawa, JP;
Kenichi Matsushita, Meguro-ku, JP;
Yusuke Kawaguchi, Miura-gun, JP;
Haruki Arai, Yokohama, JP;
Hiroshi Takei, Kawasaki, JP;
Tomohiro Kawano, Zama, JP;
Noriaki Yoshikawa, Yokohama, JP;
Morio Takahashi, Fukaya, JP;
Yasuhito Saito, Yokohama, JP;
Masahiro Urase, Himeji, JP;
Kazuo Shimokawa, Yokohama, JP;
Takashi Koyanagawa, Yokohama, JP;
Masako Ooishi, Yokohama, JP;
Tatsuya Yamada, Yokohama, JP;
Osamu Usuda, Tatsuno, JP;
Yoshiki Endo, Ibo-gun, JP;
Taiki Miura, Ibo-gun, JP;
Masaki Toyoshima, Himeji, JP;
Ichiro Omura, Yokohama, JP;
Akio Nakagawa, Fujisawa, JP;
Kenichi Matsushita, Meguro-ku, JP;
Yusuke Kawaguchi, Miura-gun, JP;
Haruki Arai, Yokohama, JP;
Hiroshi Takei, Kawasaki, JP;
Tomohiro Kawano, Zama, JP;
Noriaki Yoshikawa, Yokohama, JP;
Morio Takahashi, Fukaya, JP;
Yasuhito Saito, Yokohama, JP;
Masahiro Urase, Himeji, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.