The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2009

Filed:

Apr. 19, 2006
Applicants:

Sang Thanh Nguyen, Union City, CA (US);

Hieu Van Tran, San Jose, CA (US);

Hung O. Nguyen, Fremont, CA (US);

Phil Klotzkin, Springfield, NJ (US);

Inventors:

Sang Thanh Nguyen, Union City, CA (US);

Hieu Van Tran, San Jose, CA (US);

Hung O. Nguyen, Fremont, CA (US);

Phil Klotzkin, Springfield, NJ (US);

Assignee:

Silicon Storage Technology, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G01R 31/28 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.


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