The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2009

Filed:

Oct. 11, 2006
Applicants:

Srinivas Perisetty, Santa Clara, CA (US);

Jeffery Chow, San Jose, CA (US);

Inventors:

Srinivas Perisetty, Santa Clara, CA (US);

Jeffery Chow, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

Booster circuitry is provided that contains capacitor protection circuitry. The booster circuitry receives a digital input signal on an input line and provides a corresponding boosted digital output signal on an output line. The digital input signal may be received from an oscillator. The digital output signal may be a clock that is applied to a charge pump on a programmable logic device integrated circuit. The booster circuitry contains a metal-oxide-semiconductor capacitor. The capacitor protection circuitry ensures that the voltage across the capacitor in the booster circuit remains above a desired minimum voltage and below a desired maximum voltage during operation. The capacitor protection circuitry includes a control circuit that monitors the capacitor voltage when the booster circuit is operated while the oscillator is off and transistor-based circuitry that discharges one of the capacitor's terminals to a predetermined level when the booster circuit is operated while the oscillator is on.


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