The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2009
Filed:
Aug. 16, 2007
Kunihiko Kato, Tokyo, JP;
Kunihiko Kato, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N, having as load a Pch transistor Pand resistance element R, and an Nch transistor N, having as load a Pch transistor Pand resistance element R; and an Nch transistor Nsupplying operating current to the differential pair. The input/output terminal DQ is connected to the drain of the Nch transistor N. The output stage is operated as differential pair, in the normal operation mode (TM=L), wherein the Pch transistors P, Pare ON, a read-data signal RD is supplied to the differential pair, and a specified voltage CC is supplied to the gate of the Nch transistor N; and in the test mode (TM=H), a CMOS circuit is established wherein a read-data signal RD is supplied to the gate of the Pch transistor Pand the gate of the Nch transistor N, turning the Nch transistor NON.