The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2009

Filed:

Nov. 17, 2006
Applicants:

Peter A. Benson, Guilderland, NY (US);

Charles M. Watkins, Eagle, ID (US);

Inventors:

Peter A. Benson, Guilderland, NY (US);

Charles M. Watkins, Eagle, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material may be deposited thereinto. Also, a method for assembling a semiconductor die having a plurality of bond pads and a dielectric layer formed thereover to a carrier substrate having a plurality of terminal pads is disclosed. At least one depression may be laser ablated into the dielectric layer and a conductive material may be deposited thereinto for electrical communication between the semiconductor die and the carrier substrate. The semiconductor die may be affixed to the carrier substrate and at least one of the dielectric layer and the conductive material may remain substantially solid during affixation therebetween. The methods may be implemented at the wafer level.


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