The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2009
Filed:
Dec. 26, 2006
Applicant:
Raminda Udaya Madurawe, Sunnyvale, CA (US);
Inventor:
Raminda Udaya Madurawe, Sunnyvale, CA (US);
Assignee:
Tier Logic, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of converting designs from a field programmable gate array (FPGA) to a mask programmable gate array (MPGA), comprising: an FPGA comprising a programmable logic block array, and a plurality of programmable interconnect wires, and a bit-stream of memory data to program the FPGA; and an MPGA comprising identical layouts of the programmable logic block array and the plurality of programmable interconnect wires, wherein the bit-stream data is converted to a custom metal pattern to mask program the MPGA.