The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2009
Filed:
Jan. 18, 2006
Applicant:
Andreas Knorr, Austin, TX (US);
Inventor:
Andreas Knorr, Austin, TX (US);
Assignee:
Infineon Technologies AG, Munich, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
Abstract
Vertically stacked integrated circuits and methods of fabrication thereof are disclosed. Deep vias that provide vertical electrical connection for vertically stacked integrated circuits are formed early in the manufacturing process, before integrated circuits are bonded together to form a three dimensional integrated circuit (3D-IC).
Knorr, Andreas. (2009). Semiconductor devices and methods of manufacture thereof (U.S. Patent No. 7626257). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7626257
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile