Sram with switchable power supply sets of voltages

Abstract

A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can include a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.