The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7622779 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 24, 2009

Filed:

Sep. 09, 2003
Applicants:

Chung-kuan Cheng, San Diego, CA (US);

Hongyu Chen, La Jolla, CA (US);

BO Yao, La Jolla, CA (US);

Ronald Graham, La Jolla, CA (US);

Esther Y. Cheng, San Diego, CA (US);

Feng Zhou, Shanghai, CN;

Inventors:

Chung-Kuan Cheng, San Diego, CA (US);

Hongyu Chen, La Jolla, CA (US);

Bo Yao, La Jolla, CA (US);

Ronald Graham, La Jolla, CA (US);

Esther Y. Cheng, San Diego, CA (US);

Feng Zhou, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that each of the cells is interconnected.


Find Patent Forward Citations

Cheng, Chung-Kuan. (2009). Interconnection architecture and method of assessing interconnection architecture (U.S. Patent No. 7622779). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7622779

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