The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2009

Filed:

Oct. 02, 2007
Applicants:

Yuji Suwa, Kokubunji, JP;

Tomihiro Hashizume, Hatoyama, JP;

Masahiko Ando, Cambridge, GB;

Takeo Shiba, Kodaira, JP;

Inventors:

Yuji Suwa, Kokubunji, JP;

Tomihiro Hashizume, Hatoyama, JP;

Masahiko Ando, Cambridge, GB;

Takeo Shiba, Kodaira, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are a method for inexpensively reducing the contact resistance between an electrode and an organic semiconductor upon a p-type operation of the organic semiconductor; and a method for inexpensively operating, as an n-type semiconductor, an organic semiconductor that is likely to work as a p-type semiconductor. In addition, also disclosed are a p-cannel FET, an n-channel FET, and a C-TFT which can be fabricated inexpensively. Specifically, a p-type region and an n-type region is inexpensively prepared on one substrate by arranging an organic semiconductor that is likely to work as a p-type semiconductor in a p-channel FET region and an n-channel FET region of a C-TFT; and arranging a self-assembled monolayer between an electrode and the organic semiconductor in the n-channel FET region, which self-assembled monolayer is capable of allowing the organic semiconductor to work as an n-type semiconductor.


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