The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2009
Filed:
Sep. 24, 2007
James W. Adkisson, Jericho, VT (US);
Greg Bazan, Essex Junction, VT (US);
John M. Cohn, Richmond, VT (US);
Matthew S. Grady, Burlington, VT (US);
Thomas G. Sopchak, Williston, VT (US);
David P. Vallett, Fairfax, VT (US);
James W. Adkisson, Jericho, VT (US);
Greg Bazan, Essex Junction, VT (US);
John M. Cohn, Richmond, VT (US);
Matthew S. Grady, Burlington, VT (US);
Thomas G. Sopchak, Williston, VT (US);
David P. Vallett, Fairfax, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.