The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2009

Filed:

Dec. 15, 2006
Applicants:

Emil S. Ochotta, Mountain View, CA (US);

William W. Stiehl, Lafayette, CO (US);

Eric M. Shiflet, Boulder, CO (US);

W. Story Leavesley, Iii, Longmont, CO (US);

Inventors:

Emil S. Ochotta, Mountain View, CA (US);

William W. Stiehl, Lafayette, CO (US);

Eric M. Shiflet, Boulder, CO (US);

W. Story Leavesley, III, Longmont, CO (US);

Assignee:

XILINX, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.


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