The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2009
Filed:
Dec. 07, 2007
Woon-seong Kwon, Gyeonggi-do, KR;
Yong-hwan Kwon, Gyeonggi-do, KR;
Un-byoung Kang, Gyeonggi-do, KR;
Chung-sun Lee, Gyeonggi-do, KR;
Hyung-sun Jang, Gyeonggi-do, KR;
Woon-Seong Kwon, Gyeonggi-do, KR;
Yong-Hwan Kwon, Gyeonggi-do, KR;
Un-Byoung Kang, Gyeonggi-do, KR;
Chung-Sun Lee, Gyeonggi-do, KR;
Hyung-Sun Jang, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.