The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2009

Filed:

Feb. 20, 2004
Applicants:

Douglas J. Koslow, Boxborough, MA (US);

Leonardo Valencia, Germansville, PA (US);

Mark Harris, San Jose, CA (US);

Inventors:

Douglas J. Koslow, Boxborough, MA (US);

Leonardo Valencia, Germansville, PA (US);

Mark Harris, San Jose, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a method, mechanism, and computer usable medium for simultaneous processing or debugging of multiple programming languages. A particularly disclosed approach provides a method and mechanism for resolving the issue of simultaneous debugging of hardware represented by an HDL, e.g., Verilog or VHDL, and software, e.g., represented by C, C++, SystemC code. This approach overcomes the problem of the HDL portion of the design being inaccessible when C, C++ or SystemC code is debugged.


Find Patent Forward Citations

Koslow, Douglas. (2009). Mechanism and method for simultaneous processing and debugging of multiple programming languages (U.S. Patent No. 7617084). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7617084

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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