The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2009
Filed:
Dec. 05, 2008
Noriyuki Takahashi, Yonezawa, JP;
Masahiro Ichitani, Kodaira, JP;
Rumiko Ichitani, Legal Representative, Kodaira, JP;
Kazuhiro Ichitani, Legal Representative, Kodaira, JP;
Sachiyo Ichitani, Legal Representative, Kodaira, JP;
Noriyuki Takahashi, Yonezawa, JP;
Masahiro Ichitani, Kodaira, JP;
Rumiko Ichitani, legal representative, Kodaira, JP;
Kazuhiro Ichitani, legal representative, Kodaira, JP;
Sachiyo Ichitani, legal representative, Kodaira, JP;
Renesas Technology Corp., Tokyo, JP;
Renesas Northern Japan Semiconductor, Inc., Hokkaido, JP;
Abstract
A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.