The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2009
Filed:
Jan. 30, 2007
Eiji Nishibe, Gunma, JP;
Toshihiro Hachiyanagi, Gunma, JP;
Eiji Nishibe, Gunma, JP;
Toshihiro Hachiyanagi, Gunma, JP;
Sanyo Electric Co., Ltd., Osaka, JP;
Abstract
The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer. After the ion implantation, heat treatment (annealing) is performed at lower temperature than in heat treatment for forming the source region and the drain region.