The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2009
Filed:
Dec. 22, 2007
Hiroaki Nakaya, Kokubunji, JP;
Riichiro Takemura, Tokyo, JP;
Satoru Akiyama, Sagamihara, JP;
Tomonori Sekiguchi, Tama, JP;
Masayuki Nakamura, Tokyo, JP;
Shinichi Miyatake, Tokyo, JP;
Hiroaki Nakaya, Kokubunji, JP;
Riichiro Takemura, Tokyo, JP;
Satoru Akiyama, Sagamihara, JP;
Tomonori Sekiguchi, Tama, JP;
Masayuki Nakamura, Tokyo, JP;
Shinichi Miyatake, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.