Semiconductor memory array architecture with grouped memory cells, and method of controlling same

Abstract

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of word lines (e.g., first and second word lines) and a plurality of word line segments (e.g., first and second word line segments) wherein each word line segment is coupled to an associated word line (e.g., a first segment is associated with the first word line and a second segment is associated with the second word line). The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, wherein the body region is electrically floating, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first word line via the first word line segment and a second group of memory cells is coupled to the second word line via the second word line segment wherein at least one memory cell of the first group of memory cells is adjacent to at least one memory cell of the second group of memory cells.