Optimized charge sharing for data bus skew applications

Abstract

A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one coupled to each of the capacitive lines in the charge-sharing line set, to provide the charge recycling feature. An extra clock signal is active one cycle early during a first clock period to trigger an extra drive circuit to generate a voltage differential on a first capacitive line that is similar to the voltage level generated when real data is being propagated. The presence of an extra voltage signal on the first capacitive line takes place earlier than what would normally happen and allows for proper charge sharing between a second capacitive line and the first capacitive line. Also, there is an additional control signal associated with a last clock period following normal non-skewed charge sharing. The additional control signal triggers a reference read circuit to generate data and a voltage on the first capacitive lines similar to the voltage present during real data for proper charge sharing. The additional read and drive circuit blocks are partial copies of the normal read and drive circuits so that a matching voltage can be generated on the appropriate capacitive signal lines.