The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Apr. 08, 2008
Hao Thai Nguyen, San Jose, CA (US);
Man Lung Mui, Santa Clara, CA (US);
Seungpil Lee, San Ramon, CA (US);
Chi-ming Wang, Fremont, CA (US);
Hao Thai Nguyen, San Jose, CA (US);
Man Lung Mui, Santa Clara, CA (US);
Seungpil Lee, San Ramon, CA (US);
Chi-Ming Wang, Fremont, CA (US);
SanDisk Corporation, Milpitas, CA (US);
Abstract
A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (V) noise from the locked out bit lines to the not yet locked out bit lines.