The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Feb. 08, 2008
Paul Ying-fung Wu, Saratoga, CA (US);
Soon-shin Chee, Sunnyvale, CA (US);
Paul Ying-Fung Wu, Saratoga, CA (US);
Soon-Shin Chee, Sunnyvale, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package substrate. In one embodiment, pre-fabricated copper-clad laminate (CCL) structures are utilized as starting material for the power plane pairs, which are then integrated into a package substrate using imaging, lamination, and drilling/plating processes. In alternate embodiments, a starting material having a larger insulating layer thickness may be used to form the CCL structure, whereby a pair of metallic planes having a perforated mesh pattern are adjoined through a dielectric layer to create an effective separation distance between the metallic planes. Alternate embodiments employ plating or deposition methods to obtain a minimum separation distance between the metallic planes of a power plane pair.