The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2009

Filed:

Sep. 22, 2005
Applicants:

Bruce B. Doris, Brewster, NY (US);

Gregory Costrini, Hopewell Junction, NY (US);

Oleg Gluschenkov, Poughkeepsie, NY (US);

Meikei Ieong, Wappingers Falls, NY (US);

Nakgeuon Seong, Wappingers Falls, NY (US);

Inventors:

Bruce B. Doris, Brewster, NY (US);

Gregory Costrini, Hopewell Junction, NY (US);

Oleg Gluschenkov, Poughkeepsie, NY (US);

Meikei Ieong, Wappingers Falls, NY (US);

Nakgeuon Seong, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/04 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.


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