The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2009

Filed:

Jun. 23, 2006
Applicants:

Chang-hyun Lee, Gyeonggi-do, KR;

Jung-dal Choi, Gyeonggi-do, KR;

Chang-seok Kang, Gyeonggi-do, KR;

Yoo-cheol Shin, Gyeonggi-do, KR;

Jong-sun Sel, Gyeonggi-do, KR;

Inventors:

Chang-Hyun Lee, Gyeonggi-do, KR;

Jung-Dal Choi, Gyeonggi-do, KR;

Chang-Seok Kang, Gyeonggi-do, KR;

Yoo-Cheol Shin, Gyeonggi-do, KR;

Jong-Sun Sel, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.


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