The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Jun. 21, 2007
Tetse Jang, San Jose, CA (US);
Kevin Chung, Toronto, CA;
Jason H. Anderson, Toronto, CA;
Qiang Wang, Campbell, CA (US);
Subodh Gupta, Belmont, CA (US);
Tetse Jang, San Jose, CA (US);
Kevin Chung, Toronto, CA;
Jason H. Anderson, Toronto, CA;
Qiang Wang, Campbell, CA (US);
Subodh Gupta, Belmont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.