The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Sep. 27, 2006
Pero Subasic, Santa Clara, CA (US);
Xuejin Wang, Chandler, AZ (US);
Enis A. Dengi, Tempe, AZ (US);
Ibraz H. Mohammed, Tempe, AZ (US);
Pero Subasic, Santa Clara, CA (US);
Xuejin Wang, Chandler, AZ (US);
Enis A. Dengi, Tempe, AZ (US);
Ibraz H. Mohammed, Tempe, AZ (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.