The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Jul. 31, 2006
Thai Cheng Chua, Cupertino, CA (US);
Shankar Muthukrisnan, Plano, TX (US);
Johanes Swenberg, Los Gatos, CA (US);
Shreyas Kher, Campbell, CA (US);
Chikuang Charles Wang, San Jose, CA (US);
Giuseppina Conti, Oakland, CA (US);
Yuri Uritsky, Newark, CA (US);
Thai Cheng Chua, Cupertino, CA (US);
Shankar Muthukrisnan, Plano, TX (US);
Johanes Swenberg, Los Gatos, CA (US);
Shreyas Kher, Campbell, CA (US);
Chikuang Charles Wang, San Jose, CA (US);
Giuseppina Conti, Oakland, CA (US);
Yuri Uritsky, Newark, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.