The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Jul. 21, 2004
Deok-kee Kim, Wappingers Falls, NY (US);
Ramachandra Divakaruni, Ossining, NY (US);
Hiroyuki Akatsu, Yorktown Heights, NY (US);
George Worth, Gardiner, NY (US);
Jay Strane, Chester, NY (US);
Byeong Kim, Chester, NY (US);
Deok-kee Kim, Wappingers Falls, NY (US);
Ramachandra Divakaruni, Ossining, NY (US);
Hiroyuki Akatsu, Yorktown Heights, NY (US);
George Worth, Gardiner, NY (US);
Jay Strane, Chester, NY (US);
Byeong Kim, Chester, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.