The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Apr. 30, 2004
Applicants:
Junwei Hou, Mountain View, CA (US);
Craig Winters, Las Cruces, NM (US);
Inventors:
Junwei Hou, Mountain View, CA (US);
Craig Winters, Las Cruces, NM (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of simulating an analog mixed-signal circuit design using mixed-language descriptions includes initializing a mixed language simulation cycle, processing digital events during delta cycles at a current simulation time of the cycle, and, after the digital events are processed, determining an analog solution at the current simulation time.
Hou, Junwei. (2009). Mixed language simulation cycle for analog mixed-signal circuit design and simulation (U.S. Patent No. 7599821). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7599821
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile