The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2009
Filed:
Oct. 10, 2007
Tsu-wei Tseng, Taipei, TW;
Yu-jen Huang, Kaohsiung, TW;
Chun-hsien Wu, Hsinchu, TW;
Jin-fu LI, Pingtung County, TW;
Chien-yuan Pao, Taipei, TW;
Tsu-Wei Tseng, Taipei, TW;
Yu-Jen Huang, Kaohsiung, TW;
Chun-Hsien Wu, Hsinchu, TW;
Jin-Fu Li, Pingtung County, TW;
Chien-Yuan Pao, Taipei, TW;
Faraday Technology Corp., Hsin-Chu, TW;
Abstract
A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.