The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2009

Filed:

Oct. 27, 2006
Applicant:

Till Schlösser, Dresden, DE;

Inventor:

Till Schlösser, Dresden, DE;

Assignee:

Qimonda AG, Munich, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/8236 (2006.01); H01L 21/8234 (2006.01); H01L 21/8242 (2006.01); H01L 21/336 (2006.01); H01L 21/44 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure is disclosed. The method includes forming a peripheral circuitry in a peripheral device region, wherein the peripheral circuitry includes a peripheral transistor at least partially formed in the semiconductor substrate and having a first gate dielectric formed in a first high temperature process step. The method further includes forming a plurality of memory cells in a memory cell region, each of said memory cells including an access transistor at least partially formed in a semiconductor substrate and having a second gate dielectric formed in a second high temperature process step and having a metallic gate conductor. The first and second high temperature process steps are performed before a step of forming the metallic gate conductor.


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