The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Dec. 13, 2006
Terry Borer, Toronto, CA;
Ian Chesal, Toronto, CA;
James Schleicher, Santa Clara, CA (US);
David Mendel, Sunnyvale, CA (US);
Mike Hutton, Mountain View, CA (US);
Boris Ratchev, Sunnyvale, CA (US);
Yaska Sankar, San Jose, CA (US);
Babette Van Antwerpen, Mountain View, CA (US);
Gregg Baeckler, San Jose, CA (US);
Richard Yuan, Cupertino, CA (US);
Stephen Brown, Toronto, CA;
Vaughn Betz, Toronto, CA;
Kevin Chan, Scarborough, CA;
Terry Borer, Toronto, CA;
Ian Chesal, Toronto, CA;
James Schleicher, Santa Clara, CA (US);
David Mendel, Sunnyvale, CA (US);
Mike Hutton, Mountain View, CA (US);
Boris Ratchev, Sunnyvale, CA (US);
Yaska Sankar, San Jose, CA (US);
Babette van Antwerpen, Mountain View, CA (US);
Gregg Baeckler, San Jose, CA (US);
Richard Yuan, Cupertino, CA (US);
Stephen Brown, Toronto, CA;
Vaughn Betz, Toronto, CA;
Kevin Chan, Scarborough, CA;
Altera Corporation, San Jose, CA (US);
Abstract
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.