Computationally efficient design rule checking for circuit interconnect routing design

Abstract

Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding to each marking point includes indications of what types of interconnect elements or circuit components can be positioned at the marking point location without violating a design rule. With a dynamic caching process, once the marking computations have been completed for an element and the corresponding points in the vicinity, those values are stored in a cache. The next time the router encounters another instance of a known element-to-point relationship, the stored values are reloaded and applied to the current point.