The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2009

Filed:

Oct. 06, 2003
Applicants:

Deshanand Singh, Mississauga, CA;

Paul Mchardy, Toronto, CA;

Chris Sanford, Toronto, CA;

Gabriel Quan, Toronto, CA;

Terry Borer, Toronto, CA;

Ian Chesal, Toronto, CA;

Valavan Manohararajah, Scarborough, CA;

Ivan Hamer, Toronto, CA;

Stephen D. Brown, Toronto, CA;

Inventors:

Deshanand Singh, Mississauga, CA;

Paul McHardy, Toronto, CA;

Chris Sanford, Toronto, CA;

Gabriel Quan, Toronto, CA;

Terry Borer, Toronto, CA;

Ian Chesal, Toronto, CA;

Valavan Manohararajah, Scarborough, CA;

Ivan Hamer, Toronto, CA;

Stephen D. Brown, Toronto, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.


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