Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage

Abstract

A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.