The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Jun. 29, 2005
Ryosuke Watanabe, Isehara, JP;
Hidekazu Takahashi, Isehara, JP;
Takuya Tsurume, Atsugi, JP;
Yasuyuki Arai, Atsugi, JP;
Yasuko Watanabe, Atsugi, JP;
Miyuki Higuchi, Atsugi, JP;
Ryosuke Watanabe, Isehara, JP;
Hidekazu Takahashi, Isehara, JP;
Takuya Tsurume, Atsugi, JP;
Yasuyuki Arai, Atsugi, JP;
Yasuko Watanabe, Atsugi, JP;
Miyuki Higuchi, Atsugi, JP;
Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;
Abstract
The invention provides a laminating system in which one of second and third substrates for sealing a thin film integrated circuit is supplied to a first substrate having the plurality of thin film integrated circuit while being extruded in a heated and melted state, and further rollers are used for supplying the other substrate, receiving IC chips, separating, and sealing. Processes of separating the thin film integrated circuits provided over the first substrate, sealing the separated thin film integrated circuits, and receiving the sealed thin film integrated circuits can be continuously carried out by rotating the rollers. Thus, the production efficiency can be extremely improved.