The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2009

Filed:

May. 17, 2007
Applicants:

William Y. Chang, Williston, VT (US);

Sharon L. Von Bruns, Westford, VT (US);

Inventors:

William Y. Chang, Williston, VT (US);

Sharon L. Von Bruns, Westford, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor wafer is provided with one or more parameter scaling metric (PSM) groupings. Each PSM grouping includes a first device having a known active region geometry and further includes a set of one or more devices having active region geometry dimensions in a known relationship with the active region geometry of the first device. One or more parameter scaling metrics are calculated using measured values of one or more active region parameters of interest. The parameter scaling metric(s) can be used to quantify the stability and uniformity of a fabrication process used to make the semiconductor wafer.


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