The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Jul. 26, 2005
Chien-ting Lin, Hsin-Chu, TW;
Liang-wei Chen, I-Lan Hsien, TW;
Che-hua Hsu, Hsin-Chu Hsien, TW;
Meng-lin Lee, Chang-Hua Hsien, TW;
Hui-chen Chang, Tao-Yuan Hsien, TW;
Wei-tsun Shiau, Kao-Hsiung Hsien, TW;
Chien-Ting Lin, Hsin-Chu, TW;
Liang-Wei Chen, I-Lan Hsien, TW;
Che-Hua Hsu, Hsin-Chu Hsien, TW;
Meng-Lin Lee, Chang-Hua Hsien, TW;
Hui-Chen Chang, Tao-Yuan Hsien, TW;
Wei-Tsun Shiau, Kao-Hsiung Hsien, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.