The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2009

Filed:

Jun. 30, 2008
Applicants:

Hye Jin Seo, Icheon-si, KR;

Yong Seok Eun, Seongnam-Si, KR;

Su Ho Kim, Icheon-si, KR;

An Bae Lee, Seoul, KR;

Inventors:

Hye Jin Seo, Icheon-si, KR;

Yong Seok Eun, Seongnam-Si, KR;

Su Ho Kim, Icheon-si, KR;

An Bae Lee, Seoul, KR;

Assignee:

Hynix Semiconductor Inc., Icheon-Si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (HO) to hydrogen (H) in a range of about 1×10to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.


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