The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2009
Filed:
Feb. 25, 2002
Gyan Bhanot, Princeton, NJ (US);
Matthias A. Blumrich, Ridgefield, CT (US);
Dong Chen, Croton On Hudson, NY (US);
Paul W. Coteus, Yorktown Heights, NY (US);
Alan G. Gara, Mount Kisco, NY (US);
Mark E. Giampapa, Irvington, NY (US);
Philip Heidelberger, Cortlandt Manor, NY (US);
Burkhard D. Steinmacher-burow, Mount Kisco, NY (US);
Todd E. Takken, Mount Kisco, NY (US);
Pavlos M. Vranas, Bedford Hills, NY (US);
Gyan Bhanot, Princeton, NJ (US);
Matthias A. Blumrich, Ridgefield, CT (US);
Dong Chen, Croton On Hudson, NY (US);
Paul W. Coteus, Yorktown Heights, NY (US);
Alan G. Gara, Mount Kisco, NY (US);
Mark E. Giampapa, Irvington, NY (US);
Philip Heidelberger, Cortlandt Manor, NY (US);
Burkhard D. Steinmacher-Burow, Mount Kisco, NY (US);
Todd E. Takken, Mount Kisco, NY (US);
Pavlos M. Vranas, Bedford Hills, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.