The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Aug. 11, 2006
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of programmable tile modules that include a programmable resource, which is either programmable interconnect or programmable logic. A first characterization data is input for sub-modules of the programmable tile modules for the programmable resource. For each programmable tile module, the routing arcs of each programmable interconnect are generated. A second characterization data is input for a configuration memory cell module of the PLD design. A third characterization data is input for a configuration control module of the PLD design. A first map is generated that links each routing arc to a bit of configuration data for programming the programmable interconnect. A second map is generated that links each logic function to a bit of configuration data for programming the programmable logic.