The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2009

Filed:

Dec. 15, 2006
Applicant:

Chun-hsiang Lai, Taichung, TW;

Inventor:

Chun-Hsiang Lai, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

An ESD protection circuit includes a substrate, diode device, first snapback device, ring structure, second snapback device and a control circuit. The diode device is formed in the substrate. The first snapback device is formed in the substrate and includes a first heavy ion-doped region, a first gate and a second heavy ion-doped region. The first heavy ion-doped region is coupled to the diode device. The first gate is coupled to the second heavy ion-doped region. The ring structure is formed in the substrate and includes a third heavy ion-doped region located. The second gate is formed on the substrate between the second heavy ion-doped region and the third heavy ion-doped region to generate a second snapback device. The control circuit is connected to the third heavy ion-doped region for preventing the turn-on of a parasitic SCR formed in the substrate in a normal operation.


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