The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Apr. 09, 2007
Applicant:

Srivatsa Kundalgurki, Dresden, DE;

Inventor:

Srivatsa Kundalgurki, Dresden, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which results in an electrically conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layers, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.


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