The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Mar. 20, 2007
Applicants:

Chul-sung Kim, Kyungki-do, KR;

Byeong-chan Lee, Kyungki-do, KR;

Jong-ryeol Yoo, Kyungki-do, KR;

Si-young Choi, Kyungki-do, KR;

Deok-hyung Lee, Kyungki-do, KR;

Inventors:

Chul-sung Kim, Kyungki-do, KR;

Byeong-chan Lee, Kyungki-do, KR;

Jong-ryeol Yoo, Kyungki-do, KR;

Si-young Choi, Kyungki-do, KR;

Deok-hyung Lee, Kyungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.


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