The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2009
Filed:
Dec. 12, 2006
Satoshi Kuboyama, Tsukuba, JP;
Hiroyuki Shindou, Tsukuba, JP;
Yoshiya Ilde, Tsukuba, JP;
Akiko Makihara, Tsukuba, JP;
Satoshi Kuboyama, Tsukuba, JP;
Hiroyuki Shindou, Tsukuba, JP;
Yoshiya Ilde, Tsukuba, JP;
Akiko Makihara, Tsukuba, JP;
Japan Aerospace Exploration Agency, Tokyo, JP;
High-Reliability Engineering & Components Corporation, Ibaraki, JP;
Abstract
Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.