The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2009
Filed:
Apr. 24, 2007
Method, system, and article of manufacture for reducing via failures in an integrated circuit design
Applicants:
Xiaopeng Dong, San Jose, CA (US);
Inhwan Seo, Fremont, CA (US);
William Kao, Fremont, CA (US);
David C. Noice, Palo Alto, CA (US);
Gary Nunn, Los Gatos, CA (US);
Inventors:
Xiaopeng Dong, San Jose, CA (US);
Inhwan Seo, Fremont, CA (US);
William Kao, Fremont, CA (US);
David C. Noice, Palo Alto, CA (US);
Gary Nunn, Los Gatos, CA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of cuts in a given area. The additional vias or via cuts are inserted until a sufficient via density level has been reached.