The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2009
Filed:
May. 16, 2006
Chin-hsien Chen, Hsinchu, TW;
Ying-tso Chen, Hsinchu, TW;
Chien-hung Liu, Hsinchu, TW;
Shou-wei Huang, Hsinchu, TW;
Chin-Hsien Chen, Hsinchu, TW;
Ying-Tso Chen, Hsinchu, TW;
Chien-Hung Liu, Hsinchu, TW;
Shou-Wei Huang, Hsinchu, TW;
MACRONIX International Co., Ltd, Hsinchu, TW;
Abstract
A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.